GSD Chipset — Circuit Diagram

Coprocessor Architecture · Skill Creator × GSD × Claude Code
GSD-SKILL-CREATOR CHIPSET REV 1.49 AMIGA-INSPIRED COPROCESSOR ARCH FILESYSTEM MESSAGE BUS · EVENTENVELOPE PROTOCOL · 11 EVENT TYPES ROUTING TABLE · agent-registry.ts · 14 AGENTS · 5 TEAMS · PRIORITY QUEUES CLAUDE CPU · LLM REASONING ENGINE Claude Code Runtime · Opus 4.5 / Sonnet 4.5 200K Token Context Window Task / Skill / Bash / Read / Write / Glob AGNUS CONTEXT ENGINE · 60% DMA chip-registry.ts CONTEXT_ENGINE dma-budget.ts BudgetManager budget-stage.ts tiered alloc skill-session.ts SkillSession budget-profiles.ts per-agent cfg Signals: context-ready [16] budget-exceeded [17] schedule-tick [18] DENISE RENDER ENGINE · 15% DMA skill-pipeline.ts Pipeline skill-applicator Apply engine activation-scorer Heuristic 5-wt llm-analyzer.ts Claude self-eval generators/ skill/agent/team Ports: render-in [skill-content] render-out [formatted-output] score-out [activation-scores] PAULA I/O ENGINE · 15% DMA blitter/promoter detect offload blitter/executor child_process blitter/signals SignalBus triggers *.pid *.sld *.calc bus loops filesystem FIFO Offload: bash | node | python3 Timeout enforcement + cleanup 0 context tokens (runs external) GARY ROUTER ENGINE · 10% DMA agent-registry.ts 14 agents message-envelope EventEnvelope message-port.ts FIFO + priority routing-table 11 event types chipset.yaml per-pack config Routing: CS ME CE GL OPS → * Ack: GATE_SIGNAL, COMMAND NoAck: TELEMETRY, LEDGER EXEC KERNEL kernel.ts · scheduler.ts · dma-budget.ts · messages.ts Tick-driven execution · Prioritized round-robin · sleep()/wake() Per-engine budgets · Burst mode (5% headroom) · Message dispatch COPPER PIPELINE LIST COPROCESSOR copper/compiler.ts PlanMetadata → Pipeline copper/executor.ts WAIT · MOVE · SKIP copper/parser.ts .pipeline.yaml loader copper/lifecycle-sync GSD event binding copper/learning/ feedback → refinement BLITTER OFFLOAD ENGINE promoter.ts detect promotable executor.ts spawn child proc signals.ts completion notify Mode: offload (0 tokens) bash · node · python3 · custom GSD PROJECT MANAGEMENT LAYER orchestrator/ intent · lifecycle · gates agents/ 11 agents (exec plan verify…) commands/gsd/ 32 slash commands workflows/ discuss → plan → execute .planning/ phases · milestones · VTM SC:LEARN PIPELINE 7-STAGE KNOWLEDGE ACQUISITION Acquire Sanitize HITL Analyze Extract Dedup Merge → skill → agent → team src/learn/ · acquirer → sanitizer → hitl-gate → analyzer → extractor → dedup-prefilter → merge-engine → generators/ CHIPSET CONFIGS PER-PACK YAML DEFINITIONS brainstorm/chipset.yaml 8 agents vtm/chipset.yaml 3 agents physical-infra/chipset.yaml 6 agents knowledge/chipset.yaml 6 agents GSD-OS DESKTOP TAURI v2 · WEBGL CRT ENGINE engine/ WebGL2 + CRT pipeline boot/ chipset init animation wm/ Amiga-style windowing palette/ 32-color + copper lists $ IO RT CONTEXT WINDOW 60% context 15% render 15% I/O 10% budgetPercent: 3% (skills) hardCeiling: 8-10% maxSkills: 5 per session 32-BIT SIGNAL MASK bits 16-18 context-engine bits 19-21 render-engine bits 22-24 io-engine bits 25-27 router-engine bits 0-15 reserved (system)
Claude CPU / Exec Kernel
Agnus — Context & Budget (60%)
Denise — Render & Output (15%)
Paula — I/O & Blitter (15%)
Gary — Routing & Config (10%)
GSD — Project Management Layer
Traces — Bus & Data Lines
Board layout modeled after the Amiga A500 motherboard. Claude sits in the CPU socket (top center). The four coprocessor chips occupy the middle row, connected to the shared message bus. The Exec Kernel, Copper coprocessor, and Blitter offload engine sit below the bus. GSD's orchestrator connects as a peripheral controller. The sc:learn pipeline feeds learned skills back into the chipset. Each chip's source file locations, signal masks, and DMA percentages are annotated directly on the die. Context window budget allocation is shown in the top-left gauge. Signal bit assignments in the top-right panel. Per-pack chipset.yaml configs and the GSD-OS desktop frontend sit on the board edge.