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GSD Skill Creator
Electronics & AGC

Documentation > Specialized Systems > Electronics & AGC Education

Guide IDSS-3
AudienceStudents, Developers, Educators
PrerequisitesGS-1: Installation
Time30 minutes
DifficultyAdvanced

Electronics & AGC Education

The Apollo Guidance Computer (AGC) Block II simulator is a complete educational system for learning computer architecture through real NASA heritage technology. Rather than teaching CPU concepts in the abstract, this simulator puts you inside the machine that guided Apollo 11 to the Moon -- executing the same instruction set, managing the same priority-based scheduler, and reproducing the same 1202 alarm that nearly aborted the lunar landing. Every component is implemented as pure TypeScript in src/agc/ with full test coverage, making the architecture transparent and explorable.

AGC Overview

The AGC was a 15-bit computer built by MIT's Instrumentation Laboratory for NASA's Apollo program. It ran at 2.048 MHz, used ones' complement arithmetic (where negative zero is a distinct value), and packed its entire operating system, guidance equations, and user interface into roughly 36K words of hand-woven core rope memory. During Apollo 11, the AGC famously handled a radar data overflow by shedding low-priority tasks through its restart protection system -- a design decision that saved the mission.

The simulator recreates the AGC Block II at the instruction level. It is not a hardware emulator that simulates individual logic gates, but a functional simulator that reproduces the behavior of every instruction, every interrupt, and every scheduling decision with cycle-accurate timing. The result is an educational platform where students can write AGC assembly, step through execution, observe the executive's scheduling decisions, and reproduce the conditions that triggered the Apollo 11 alarms.

CPU Architecture

The simulated CPU (src/agc/cpu.ts) implements 38 instructions organized into four categories:

  • 15 basic instructions -- TC (transfer control), CCS (count/compare/skip), TCF (transfer control to fixed), DAS (double-precision add to storage), LXCH (L register exchange), INCR (increment), ADS (add to storage), CA (clear and add), CS (clear and subtract), INDEX (index next instruction), DXCH (double exchange), TS (transfer to storage), XCH (exchange), AD (add), MASK (bitwise AND).
  • 18 extracode instructions -- Accessed via the EXTEND prefix: READ, WRITE, RAND, WAND, ROR, WOR, RXOR (I/O channel operations), DV (divide, 6 MCTs), BZF (branch zero to fixed), MSU (modular subtract), QXCH (Q register exchange), AUG (augment), DIM (diminish), DCA (double clear and add), DCS (double clear and subtract), SU (subtract), BZMF (branch zero or minus to fixed), MP (multiply, 3 MCTs).
  • 5 special instructions -- EXTEND (set extracode mode), INHINT (inhibit interrupts), RELINT (release interrupts), RESUME (return from interrupt), NOOP (no operation).

The ALU (src/agc/alu.ts) operates in ones' complement arithmetic on 15-bit words. This means the value -0 (all ones, octal 77777) is distinct from +0 (all zeros). The ALU provides addition, subtraction, negation, complement, absolute value, increment, decrement, diminish, multiply, divide, and double-precision add operations, all respecting ones' complement overflow semantics where an overflow produces a corrected result and sets the overflow flag.

Bank-Switched Memory

The memory system (src/agc/memory.ts) implements the AGC's bank-switching scheme across a 12-bit address space:

  • Erasable memory (RAM) -- 2,048 words across 8 banks of 256 words each. The first 256 words (bank 0) are unswitched (always visible). Banks 1-7 are accessed through EBANK switching, which maps one bank at a time into the 0400-0777 address window.
  • Fixed memory (ROM/core rope) -- 36,864 words across 36 banks of 1,024 words each. Banks 02 and 03 are fixed-fixed (always visible at addresses 2000-3777). Banks 00-37 are accessed through FBANK switching with superbank selection, mapped into the 4000-7777 address window.
  • Register space -- Addresses 0000-0017 map to hardware registers rather than memory, providing zero-overhead access to the accumulator, L register, Q register, and bank registers.

Interrupt System

The interrupt controller (src/agc/interrupts.ts) implements 10 hardware interrupt vectors, prioritized from highest (1) to lowest (10):

  • BOOT (1) -- System initialization at address 04000
  • T6RUPT (2) -- Time 6 timer (used for fine guidance timing)
  • T5RUPT (3) -- Time 5 timer (autopilot cycle)
  • T3RUPT (4) -- Time 3 timer (task scheduling)
  • T4RUPT (5) -- Time 4 timer (DSKY display refresh)
  • KEYRUPT1/KEYRUPT2 (6-7) -- DSKY keyboard input
  • UPRUPT (8) -- Uplink data from ground
  • DOWNRUPT (9) -- Downlink telemetry complete
  • RADARRUPT (10) -- Radar data ready

Interrupt entry saves the program counter (Z) and bank register (BB) to ZRUPT/BRUPT, then jumps to the vector address. The RESUME instruction restores execution context. INHINT and RELINT control whether interrupts can be serviced. The controller prevents nested interrupts -- if an ISR is active, new interrupts remain pending until RESUME executes.

Timing Model

The timing system (src/agc/timing.ts) provides cycle-accurate simulation based on the AGC's 2.048 MHz master oscillator. Each Memory Cycle Time (MCT) is 11.72 microseconds. Different instructions consume different numbers of MCTs: TC and TCF take 1 MCT, most arithmetic and logic instructions take 2 MCTs, DAS and DXCH take 3 MCTs, and DV (divide) takes 6 MCTs. The timing model tracks total MCTs elapsed since simulation start and provides conversion functions to microseconds, milliseconds, and seconds.

Executive System

The Executive (src/agc/executive.ts) is the AGC's operating system kernel -- a priority-based cooperative job scheduler managing 8 core sets (numbered 0-7). Each core set stores the complete execution context for one job, including register state, priority level, and lifecycle phase (FREE, DORMANT, RUNNABLE, RUNNING, SLEEPING).

  • Job creation -- NOVAC creates a lightweight job with no VAC area. FINDVAC creates a job with a 44-word Variable Area Cluster (VAC) for sustained computation. Only 5 VAC areas are available; exhausting them triggers alarm 1201.
  • Scheduling -- Priority 0 is highest (guidance equations), priority 7 is lowest (display updates). The scheduler always selects the runnable job with the lowest priority number. Ties are broken by lowest core set number for deterministic behavior.
  • Core set 0 -- Reserved for the idle job, which always exists and runs at the lowest priority. When no other jobs are runnable, the idle job executes.
  • Alarm 1202 -- When all 8 core sets are occupied and a new job is requested, the Executive generates alarm 1202 (Executive overflow). This is the famous alarm from Apollo 11 that the restart protection system handled by shedding lower-priority tasks.

Waitlist

The Waitlist (src/agc/waitlist.ts) is a timer-driven task queue with 9 entries. Unlike Executive jobs, waitlist tasks fire at precise times (based on hardware timer interrupts) and execute short code sequences before returning control to the Executive. The waitlist is the mechanism behind all AGC timing functions: guidance cycles, autopilot updates, display refresh, and telemetry scheduling.

DSKY Interface

The DSKY (Display and Keyboard) is the astronaut's interface to the AGC. The simulator implements three components:

  • Display model (src/agc/dsky-display.ts) -- Emulates the DSKY's electroluminescent display with program number, verb/noun registers, three signed 5-digit data registers, and status indicator lights (COMP ACTY, UPLINK ACTY, TEMP, KEY REL, RESTART, OPR ERR, TRACKER, ALT, VEL, NO ATT, GIMBAL LOCK, STBY, PROG).
  • Keyboard (src/agc/dsky-keyboard.ts) -- Implements the 19-key DSKY keypad: digits 0-9, VERB, NOUN, PRO (proceed), KEY REL (keyboard release), ENTR (enter), CLR (clear), RSET (reset), and +/- signs.
  • VERB/NOUN commander (src/agc/dsky-commander.ts) -- The protocol layer that translates VERB-NOUN pairs into AGC operations. VERB 16 NOUN 65 displays the current time, VERB 37 changes the active program, and so on.

Developer Tools

The src/agc/tools/ directory provides four development tools for working with AGC programs:

  • yaYUL assembler (assembler.ts) -- Assemble AGC assembly language source into binary images. Supports the full AGC instruction set with labels, bank declarations, and address computation. Named after the original YUL assembler used at MIT.
  • Debugger (debugger.ts) -- Step through AGC execution one instruction at a time. Inspect registers, memory, interrupt state, and executive job queues. Set breakpoints on addresses, instructions, or conditions (e.g., break on alarm 1202).
  • Disassembler (disassembler.ts) -- Reverse-engineer AGC binary images back to assembly mnemonics. Handles bank switching and extracode prefixes, producing readable output with addresses and labels.
  • Rope loader (rope-loader.ts) -- Load AGC program images (core rope memory dumps) into the simulator's fixed memory. Supports loading historical Luminary and Colossus program binaries.
  • Validation suite (validation.ts) -- Comprehensive instruction-level validation against expected AGC behavior, ensuring simulator fidelity.

Curriculum

The curriculum (src/agc/curriculum/) provides structured learning through 11 chapters and 8 hands-on exercises, managed by a curriculum runner (runner.ts) that tracks progress and enforces prerequisites.

Chapters:

  • Chapter 1: Orientation -- Introduction to the AGC and its role in Apollo
  • Chapter 2: Hardware -- Physical architecture, integrated circuits, core rope
  • Chapter 3: Instruction Set Architecture -- The 38 instructions in detail
  • Chapter 4: Assembly Language -- Writing and assembling AGC programs
  • Chapter 5: Executive and Waitlist -- Job scheduling and timer tasks
  • Chapter 6: DSKY -- Display, keyboard, and VERB/NOUN interface
  • Chapter 7: Interpreter -- The AGC's double-precision math coprocessor
  • Chapter 8: Guidance -- Navigation equations and orbital mechanics
  • Chapter 9: Failsafe Design -- Restart protection and error recovery
  • Chapter 10: Apollo 11 -- The mission timeline and the 1202 alarm
  • Chapter 11: AGC to GSD -- How AGC design principles influenced skill-creator

Exercises:

  • Exercise 1: Hello DSKY -- Display your first message on the DSKY
  • Exercise 2: Countdown -- Implement a countdown timer using the waitlist
  • Exercise 3: Calculator -- Build an arithmetic calculator with VERB/NOUN input
  • Exercise 4: Blinker -- Create blinking indicator lights using interrupts
  • Exercise 5: Scheduler -- Write a multi-job program using the Executive
  • Exercise 6: Priority -- Explore priority inversion and scheduling behavior
  • Exercise 7: Restart -- Implement restart protection for a running program
  • Exercise 8: Capstone 1202 -- Reproduce the Apollo 11 alarm scenario

Supporting Study Packs

The infra/packs/agc/ directory contains study materials and reference archives. The archive includes a catalog of AGC-related documents with cross-references and curated reading paths that guide students through primary sources in a logical order. Study packs provide architecture mapping documents, curriculum integration guides, design recommendation analysis, and simulation architecture documentation that connects the historical AGC design to the simulator implementation.

Learn Mode

The learn mode system (src/agc/learn-mode.ts) provides progressive disclosure of AGC architecture concepts. Instead of exposing the full complexity upfront, learn mode introduces subsystems incrementally -- starting with basic instruction execution, then adding memory banking, interrupts, the executive, and finally the DSKY. Each disclosure level unlocks new concepts while reinforcing previously learned material, making the AGC approachable for students encountering 1960s computer architecture for the first time.

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